Low voltage amplifier

ABSTRACT

An operational amplifier is configured for low voltage operation and better compliance. An exemplary operational amplifier comprises a folded-cascode amplifier with a class-AB biased output stage configured for low voltage operation. The exemplary output stage includes a class-AB control loop being controlled for the upper output device, and with the complementary, lower output device being driven through an additional gain configuration to allow for the necessary compliance voltage. In addition, the lower output device can be configured to operate with a low gate-source voltage.

FIELD OF INVENTION

[0001] The present invention relates to amplifiers. More particularly,the present invention relates to a low voltage amplifier.

BACKGROUND OF THE INVENTION

[0002] The demand for improved operational amplifiers, and in particularlow power, operational amplifier circuits for high-precision dataacquisition and instrumentation applications, such as multi-channel dataacquisition systems, audio processing, test equipment and other consumerelectronics applications continues to increase. Such operationalamplifier circuits generally include an input stage circuit and anoutput stage circuit comprised of various amplifier devices and othercurrent sources.

[0003] The input stage of many operational amplifier circuits, forexample one comprising a differential pair arrangement of transistors,is configured for sensing a differential input voltage, which mayrealize inherent errors with offset voltage, bias current, offsetvoltage drift, and noise. The design of the input stage is typicallyaimed at minimizing these errors, while maintaining low currentconsumption, and with a large portion of the rail-to-rail input rangebeing made available for common-mode signals.

[0004] Output stages are generally configured to provide a loadimpedance Z_(L) with a desired output voltage V_(OUT) and currentI_(OUT), resulting in an output power P_(OUT)=V_(OUT)I_(OUT). Thetypical main requirements of output stages are to provide negative andpositive output currents at high current efficiency, an output voltagerange that efficiently uses the full rail-to-rail range, i.e., from thenegative supply rail to the positive supply rail, low distortion, andgood high-frequency performance.

[0005] Class-AB biasing is often used to improve performance of outputstage devices due to the ability to eliminate cross-over distortion bybiasing the output transistors at a small, but finite, current. Class-ABbiasing is similar to class-A biasing in that the output transistors aremaintained “on”, and similar to class-B biasing in that the outputtransistors are biased at a much smaller current than the peak currentdelivered to the load. Class-AB biasing can be configured withfeedforward biasing or with feedback biasing. Feedforward biasing isutilized when the biasing is fixed by components in series or inparallel with the signal path, while in feedback biasing uses a feedbackloop to provide the class-AB biasing.

[0006] With reference to FIG. 1, an operational amplifier circuit 100comprising an input stage 102 and an output stage 104 is illustrated asseparate stages, which can be directly connected, or coupled throughother stages. Such a class-AB configuration is often referred to asdirect class-AB biasing.

[0007] Input stage 102 comprises a differential pair of transistors M₁and M₂. The difference in input current from a source I₁ at the sourcesof transistors M₁ and M₂ is derived at the drains as signal currents,SIGNAL₁ and SIGNAL₂. Difference currents SIGNAL₁ and SIGNAL₂ can be fedinto multiple stage applications with appropriate level shifting, e.g.,folded cascode or other stage applications, such as output stage 104.

[0008] Output stage 104 comprises a class-AB biasing configurationincluding biasing transistors B₁-B₄, a pair of complementary signaldevices M₃ and M₄, and a pair of output devices, M₅ and M₆. Output stage104 is configured to source current in output device M₅ and to sinkcurrent through output device M₆. It is desirable for output stage 104to be able to fully swing from the positive rail to the negative rail,i.e., from V_(S) ⁺ to ground. This generally requires output devices M₅and M₆ to be driven as common source devices. As common source devices,it is difficult to provide biasing when no current is flowing throughoutput devices M₅ and M₆. Further, when there is little or no outputcurrent at zero load, output devices M₅ and M₆ must still maintain a lowdynamic output impedance. Without class-AB biasing, the output currentcould not go to zero, or the output impedance would be extremely high.However, the class-AB biasing configuration facilitates zero currentunder a zero load condition.

[0009] For example, biasing transistors B₁ and B₂ are connected inseries and configured with a controlled current source I₂ to supply twogate-source voltages V_(GS) to the gate of transistor M₃. Transistor M₃comprises a source follower that supplies current to the gate oftransistor M₅, thus providing a first, upper controlled V_(GS) loop,with the gate-source voltages V_(GS) of biasing transistors B₁ and B₂equaling the gate-source voltages V_(GS) of transistors M₃ and M₅. Thecurrent flow within the upper V_(GS) loop is defined by the areas andcurrent flow within the devices. A current source I₄ is configured toprovide a controlled current through transistor M₃. Thus with controlledcurrent provided through biasing transistors B₁ and B₂ and transistorM₃, the current flow in transistor M₅ can be substantially controlled.Similarly, a second, lower controlled V_(GS) loop is provided withbiasing transistors B₃ and B₄, transistor M₄, and a controlled currentsource I₅ to control the nominal current flow in transistor M₆.

[0010] During operation, when transistor M₅ sources (or supplies) morecurrent, the gate-source voltage V_(GS) of transistor M₅ increases;since the gate of transistor M₃ is constant, the gate-source voltageV_(GS) of transistor M₃ must decrease, resulting in less current flowthrough transistor M₃. Therefore, some of the current supplied to a node106 must be diverted instead to transistor M₄, resulting in thegate-source voltage V_(GS) of transistor M₄ getting larger, thusdecreasing or cutting off the gate-source voltage V_(GS) of transistorM₆, i.e., as transistor M₅ sources more current, transistor M₆ is cutoff. Conversely, as transistor M₆ sinks (or requires) more current,transistor M₅ is cut off. For no load current, half of the current intonode 106 flows through transistor M₃ and the other half through thedrain of transistor M₄ to supply bottom current source I₅, resulting innominal biasing of output devices M₅ and M₆, i.e., a quiescent currentcondition with zero load current.

[0011] Unfortunately, for the upper and lower loops of output stage 104to effectively bias the gates of transistors M₃ and M₄, at least twogate-source voltage V_(GS) are needed. For typical CMOS processes, thistwo gate-source voltage V_(GS) condition requires at least two volts ormore, which is significantly higher than the low voltage operation,e.g., 1.8 volt or less, that is being demanded in current applications.

SUMMARY OF THE INVENTION

[0012] In accordance with various aspects of the present invention, anoperational amplifier is configured for low voltage operation and bettercompliance. In accordance with an exemplary embodiment, an operationalamplifier comprises a folded-cascode amplifier with a class-AB biasedoutput stage configured for low voltage operation. The exemplary outputstage includes a class-AB control loop being controlled for the upperoutput device, and with the complementary, lower output device beingconfigured with an additional gain arrangement to allow for thenecessary compliance voltage. The lower output device is configured tooperate with a low gate-source voltage without significantly affectingthe load impedance seen by a difference current received from an inputstage. This configuration significantly increases the gain of theoperational amplifier.

[0013] In accordance with an exemplary embodiment, the upper devices ofthe output stage can be configured with a cascoded mirror and a class-ABcontrol loop driven by a charge pump to meet and/or exceed compliancevoltage requirements for the upper devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] A more complete understanding of the present invention may bederived by referring to the detailed description and claims whenconsidered in connection with the Figures, where like reference numbersrefer to similar elements throughout the Figures, and:

[0015]FIG. 1 illustrates a schematic diagram of a prior art operationalamplifier circuit;

[0016]FIG. 2 illustrates a block diagram of an exemplary operationalamplifier circuit in accordance with an exemplary embodiment of thepresent invention;

[0017]FIG. 3 illustrates a schematic diagram of an exemplary operationalamplifier circuit in accordance with an exemplary embodiment of thepresent invention; and

[0018]FIG. 4 illustrates a schematic diagram of another exemplaryoperational amplifier circuit in accordance with an exemplary embodimentof the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION

[0019] The present invention may be described herein in terms of variousfunctional components. It should be appreciated that such functionalcomponents may be realized by any number of hardware or structuralcomponents configured to perform the specified functions. For example,the present invention may employ various integrated components, such asbuffers, current mirrors, and logic devices comprised of variouselectrical devices, e.g., resistors, transistors, capacitors, diodes andthe like, whose values may be suitably configured for various intendedpurposes. In addition, the present invention may be practiced in anyintegrated circuit application. Such general applications that may beappreciated by those skilled in the art in light of the presentdisclosure are not described in detail herein. However for purposes ofillustration only, exemplary embodiments of the present invention willbe described herein in connection with a low voltage amplifierapplication. Further, it should be noted that while various componentsmay be suitably coupled or connected to other components withinexemplary circuits, such connections and couplings can be realized bydirect connection between components, or by connection through othercomponents and devices located thereinbetween.

[0020] Maintaining a large saturation voltage V_(DSAT) forfolded-cascode loads is required for best noise and offset performance.Unfortunately, prior methods of “direct” class AB biasing areimpractical for low voltage operation. However, in accordance withvarious aspects of the present invention, an operational amplifier isconfigured for low voltage operation and better compliance, i.e., withhigher drain-saturated voltages V_(DSAT) being attainable.

[0021] In accordance with an exemplary embodiment, an operationalamplifier comprises a folded-cascode amplifier having a class-AB biasedoutput stage configured for low voltage operation. The exemplary outputstage includes a class-AB control loop being controlled for the upperoutput device, and with the complementary, lower output device beingconfigured with an additional gain arrangement to allow for thenecessary compliance voltage. In other words, only an upper class-ABloop is controlled, with a reduced gate-source voltage V_(GS) requiredfor the lower output device, and thus permitting lower voltageoperation.

[0022] For example, with reference to FIG. 2, a block diagram of anexemplary operational amplifier 200 is illustrated. Operationalamplifier 200 comprises a folded-cascode amplifier having an input stage202 and an output stage 204. Input stage 202 is configured to providedifference current signals, SIGNAL₁ and/or SIGNAL₂, to output stage 204,either directly, or through one or more stages in between. While inputstage 202 can comprise various configurations, in the exemplaryembodiments input stage 202 comprises a differential pair oftransistors, e.g., FET, bipolar or other transistor-types, configured toreceive a differential input voltage, V_(IN) ⁺ and V_(IN) ^(−.) Forexample, with momentary reference to FIG. 3, an input stage 302 cancomprise a differential pair of transistors M₁ and M₂. The difference ininput current from a source I₁ at the input terminals, e.g., sources, oftransistors M₁ and M₂ is derived at the output terminals, e.g., drains,as signal currents, SIGNAL₁ and SIGNAL₂. Difference currents SIGNAL₁and/or SIGNAL₂ can be fed into multiple stages with appropriate levelshifting, e.g., with folded cascode or other stages, or fed directly tooutput stage 204.

[0023] Output stage 204 is configured to provide an output voltageV_(OUT) under low voltage conditions, i.e., at approximately 1.8 voltsor less. Output stage 204 comprises a class-AB biased output stageconfigured for low voltage operation. Output stage 204 includes a pairof input devices 205 and 207 configured to receive at least one ofdifference currents SIGNAL₁ and SIGNAL₂ from input stage 202, andconfigured with biasing devices 214 and 216. Output stage 204 alsoincludes a pair of output devices 206 and 208 configured for sourcingand sinking current to a load. A class-AB control loop 210 comprisingdevices 214, 205 and 206 is configured for controlling upper outputdevice 206, while complementary, lower output device 208 includes anadditional gain configuration comprising a direct signal path to allowfor the necessary compliance voltage. For example, lower output device208 is configured to operate with a low voltage, e.g., a low gate-sourcevoltage, without significantly affecting the load impedance seen bydifference current SIGNAL₁ due to output stage 204. This configurationsignificantly increases the gain of operational amplifier 200.

[0024] Output stage 204 can be configured in various arrangements. Forexample, with reference to an exemplary embodiment in FIG. 3, an outputstage 304 comprises biasing transistors B₁ and B₃, signal devices M₃,M₄, M₇ and M₈, and a pair of complementary output devices M₅ and M₆.Output stage 304 is configured to allow the sourcing of a large currentin output device M₅ and to allow the sinking of a large current throughoutput device M₆.

[0025] Output stage 304 comprises an upper control loop for the upperdevices, i.e., a control loop comprising devices B₁, M₃, M₇ and M₅, forcontrolling the signal current through output device M₅ to an outputterminal V_(OUT). In the exemplary embodiment, the upper control loopcomprises a PMOS class-AB control loop. Biasing device B₁ comprises adiode-connected transistor configured to provide a gate-source voltageV_(GS) to drive the control terminal, e.g., the gate, of signal deviceM₃, with the drain of biasing device B₁ connected to a current sourceI₂. Signal device M₃ has a source coupled to a node 306 from which acurrent source I₄ and difference current signal SIGNAL₂ are received,and a drain coupled to the drain of lower signal device M₈. Signaldevice M₇ comprises a diode-connected transistor having a gate coupledto the gate of upper output device M₅, with the source of signal deviceM₇ coupled to a node 306 and a drain coupled to the drain of signaldevice M₄. Output device M₅ further comprises a source coupled to anupper rail supply voltage V_(S) ⁺, and a drain coupled to an outputterminal V_(OUT).

[0026] To meet and/or exceed compliance voltage requirements for theupper devices, output stage 304 can include a charge pump configured toprovide additional voltage beyond upper rail supply V_(S) ⁺. Forexample, a charge pump can be coupled to current source I₄ that drivessignal device M₇ and signal device M₃, for example by connection toupper rail supply V_(S) ⁺ or through a current mirror circuit, thusimproving compliance for the upper devices.

[0027] As for the lower devices, output stage 304 does not include acomplementary lower control loop, i.e., a control loop operating thesame as the upper class-AB control loop. Instead, output stage 304 isconfigured with an additional gain arrangement for driving output deviceM₆ such that voltage changes at the gate of output device M₆ do notsignificantly affect the load impedance seen by difference currentSIGNAL₁ due to output stage 304. As a result, the gain of operationalamplifier 300 is significantly increased. In other words, only an upperclass-AB loop is controlled, thus permitting lower voltage operation.

[0028] Biasing device B₃ comprises a diode-connected transistorconfigured to provide a gate-source voltage V_(GS) to drive the gate ofdevice signal M₄, with the drain of biasing device B₃ connected to acurrent source I₃. Signal device M₄ has a source coupled to a node 308from which a current source I₅ and difference current signal SIGNAL₁ arecoupled, and a drain coupled to the drain of signal device M₇. Signaldevice M₈ has a source coupled to node 308, and thus to current sourceI₅, a drain coupled to the drain of signal device M₃, and a gate coupledto the gate of signal device M₄. Thus, with their respective sources andgates connected together, signal device M₄ and signal device M₈ operateas a current splitter configuration for current source I₅ and SIGNAL₁.

[0029] Current source I₅ is configured to have increased compliancevoltage. For example, with reference to FIG. 3C, a current sourcecomprises a transistor M₁₀ having a voltage from a node 308 to groundcomprising the compliance voltage, V_(DSAT). For good DC performance andoperation at a high impedance condition, it is desirable for thecompliance voltage V_(DSAT) to be approximately greater than thegate-source voltage V_(GS) less the transistor threshold voltage V_(T),i.e., V_(DSAT)˜>V_(GS)−V_(T), with a range between, for example,approximately 1 volt to approximately 300 millivolts. Thus, currentsource I₅ is configured to have increased compliance voltage rangingbetween approximately 1 volt to approximately 300 millivolts.

[0030] Output device M₆ comprises a large device to facilitate highcurrent flow at output terminal V_(OUT) when large sinking currents arerequired. However, to facilitate low current flow when the currentrequirements at output terminal V_(OUT) are low, output device M₆ isconfigured with a lower gate-source voltage V_(GS), for exampleapproximately 600 mV or less. Output device M₆ includes a source coupledto ground, and a drain coupled to output terminal V_(OUT). In addition,the gate of output device M₆ is coupled in a direct signal path througha node 312 to the drain of signal device M₃. As a result, the compliancevoltage V_(DSAT) of current source I₅ can be increased to approximately300 mV or more without increasing the voltage at the gate of outputdevice M₆.

[0031] Moreover, unlike prior art output stage 104, changes in the gatevoltage of output device M₆ does not detrimentally affect the loadimpedance seen by difference current SIGNAL₁ due to output stage 304.Instead, the gate voltage of output device M₆ is controlled by theadditional gain configuration comprising a direct signal path from thedrain of upper signal device M₃. In addition, through the currentsplitter configuration of signal device M₄ and signal device M₈, whichin effect provide an amplifier function, a high gain can be realized atthe gate of output device M₆, e.g., in the order of approximately 10× to100× or more. Thus, the configuration of the lower devices of outputstage 304 facilitates lower voltages, better compliance, and increasedgain.

[0032] During operation of output stage 304, for output device M₅ tosource a large current, the gate-source voltage V_(GS) of output deviceM₅ is increased. To increase the gate-source voltage V_(GS) of outputdevice M₅, the proportion of current from current source I₄ throughsignal device M₇ is increased (to increase the gate-source voltageV_(GS) of transistor M₇), and thus the proportion of current fromcurrent source I₄ through signal device M₃ is decreased (to decrease thegate-source voltage V_(GS) of transistor M₃). The proportion of currentfrom current source I₄ through signal device M₇ can be increased bychanging the rates of current from current source I₅ through signaldevice M₄ and signal device M₈, e.g., with more current through signaldevice M₄ and less current through signal device M₈. To provide morecurrent through signal device M₄ and less current through signal deviceM₈, the voltage at node 312 is suitably reduced, thus decreasing orcutting off the gate-source voltage V_(GS) of output device M₆, i.e., asoutput device M₅ sources more current, output device M₆ is cut off.

[0033] On the other hand, as output device M₆ sinks a large current, thecurrents through devices M₄, M₈, M₃ and M₇ require substantially lesschange such that output device M₅ is only slightly queued down from ano-load condition.

[0034] Thus, for no load current, half of the current into node 306flows through transistor M₃ and the other half through the drain oftransistor M₄ to supply bottom current source I₅, resulting in nominalbiasing of output devices M₅ and M₆, i.e., a quiescent current conditionwith zero load current. The current in output devices M₅ and M₆ can beconfigured at the quiescent current level and provide an appropriatelevel of current at output terminal V_(OUT) through an external feedbackpath in operational amplifier 300. The external feedback path canprovide for small differences in differential input voltage, V_(IN) ⁺and V_(IN) ⁻ to provide small differences in currents SIGNAL₁ andSIGNAL₂.

[0035] With reference to FIG. 4, a voltage amplifier 400 is illustratedin accordance with another exemplary embodiment of the presentinvention. Voltage amplifier 400 comprises a folded-cascode amplifierhaving an input stage 402 and an output stage 404. Input stage 402comprises a differential input stage configuration including adifferential pair of transistors M₁ and M₂, configured for receivingdifferential input signals V_(IN) ⁺ and V_(IN) ⁻, respectively. Thesource terminals of transistors M₁ and M₂ are controlled by an inputcurrent from a current source I₁. The difference in input current fromcurrent source I₁ at the sources of transistors M₁ and M₂ is derived attheir respective drains as signal currents, SIGNAL₁ and SIGNAL₂.Difference currents SIGNAL₁ and SIGNAL₂ can be fed into to output stage404 through various stages or devices with appropriate level shifting.

[0036] Current source I₁ can be suitably driven by a charge pump atterminal V_(PUMP), e.g., by connection of a source of a transistor M₃₄to terminal V_(PUMP) which is approximately two volts above the upperrail supply, or driven directly by the upper rail supply. However,providing a charge pump, e.g., at approximately two volts above theupper rail supply, can allow input stage 402 to realize fullrail-to-rail operation.

[0037] Output stage 404 comprises biasing transistors B₁ and B₃, signaldevices M₃, M₄, M₇ and M₈ and a pair of complementary output devices M₅and M₆. Output stage 404 is configured to allow the sourcing of a largecurrent in upper output device M₅ and to allow the sinking of a largecurrent through lower output device M₆. Output stage 404 is configuredwith an additional gain arrangement for driving output device M₆ suchthat a reduced gate-source voltage V_(GS) is needed for lower outputdevice M₆, thus allowing low voltage operation of output stage 404.

[0038] A PMOS class-AB control loop comprising devices B₁, M₃, and M₇ isprovided for controlling the signal current through upper output deviceM₅ to an output terminal V_(OUT), i.e., the gate of output device M₅controlled by the PMOS loop through devices M₇ and M₃, anddiode-connected biasing device B₁. The drain of biasing device B₁ isconnected to a current source I₂, comprising a transistor M₁₈. A cascodetransistor M₁₉ coupled to transistor M₁₈ can facilitate a high outputimpedance for current source I₂.

[0039] Signal devices M₃ and M₇ have sources coupled to a node 406 fromwhich difference current signal SIGNAL₂ is received. Current signalSIGNAL₂ is provided through a signal path from the drain of transistorM₂, through a folded-cascode stage comprising current source transistorM₁₀, and cascoding devices M₁₁ and M₁₂, and through a current mirror 410(representative of a current source I₄) to node 406. Current mirror 410comprises a cascoding configuration including transistors M₁₃, M₁₄, M₁₅and M₁₆. In the exemplary embodiment, current mirror 410 is coupled tocharge pump terminal V_(PUMP). Current mirror 410 is configured withtransistor M₁₄ having a gate connected back to the drain of transistorM₁₃.

[0040] Lower output device M₆ is not controlled by a class-AB controlloop, but rather is driven by a direct signal path. Output device M₆ hasa source connected to lower rail supply V_(S) ⁻, a drain coupled to anoutput terminal V_(OUT), and a gate coupled to the drain of transistorM₃ through a node 412. Lower devices B₃, M₈ and M₄ are configured in again configuration to enable output device M₆ to have a low gate-sourcevoltage without significantly affecting the load impedance seen bydifference current SIGNAL₁ due to output stage 404. The gainconfiguration of lower devices B₃, M₈ and M₄ significantly increases thegain of operational amplifier 400. Biasing device B₃ is diode-connected,with the gate-drain connected to the gates of devices M₈ and M₄. Thegate-drain of biasing device B₃ is further connected to a current sourceI₃. Signal device M₄ and device M₈ have sources coupled to a node 408from which difference current signal SIGNAL₁ is received. Current signalSIGNAL₁ is provided through a signal path from the drain of transistorM₁, to the drain of a transistor M₁₇ (representative of a current sourceI₅).

[0041] Output stage 404 can also comprise various other devices forbiasing, cascoding and for shutting down. For example, a first biasingcircuit comprising transistors M₂₂ and M₂₃ coupled to bias terminalI_(BIAS1) is provided for generation of current sources I₄ and I₅, whilea second biasing circuit comprising transistors M₂₄, M₂₅, M₂₆, M₂₇ andM₃₀ coupled to bias terminal I_(BIAS1) is provided for generation ofcurrent sources I₁ and I₂. To provide current source I₁, a currentmirror 420 comprising transistors M₃₃ and M₃₄ can also be provided tomirror current from the second biasing circuit. In various embodiments,a shutdown circuit can also be included, for example, with the shutdowncircuit comprising transistors M₃₁ and M₃₂ coupled to a signal SHUTDOWN.

[0042] Compensation for operational amplifier 400 can be providedthrough compensation capacitors C₀, C₁, and C₂ and a resistor R₀.Compensation capacitors C₀ and C₁ are coupled between the gates ofoutput devices M₅ and M₆, i.e., between the gate-drain connection ofsignal device M₇ and node 412. In the exemplary embodiment, compensationcapacitors C₀ and C₁ have approximately 3.6 pF of capacitance. Aresistor R₀ is connected to the drain of output device M₆ and in betweencompensation capacitors C₀ and C₁. Further, another compensationcapacitor C₂ can be coupled across the gate-drain terminals of outputdevice M₆.

[0043] The present invention has been described above with reference tovarious exemplary embodiments. However, those skilled in the art willrecognize that changes and modifications may be made to the exemplaryembodiments without departing from the scope of the present invention.For example, the various components may be implemented in alternateways, such as, for example, by implementing bipolar or JFET devices forthe various devices. In addition, one or more additional stages may beincluded at the input or output stages in accordance with variousexemplary embodiments. Further, the various exemplary embodiments can beimplemented with other types of operational amplifier circuits inaddition to the circuits illustrated above. These alternatives can besuitably selected depending upon the particular application or inconsideration of any number of factors associated with the operation ofthe system. Moreover, these and other changes or modifications areintended to be included within the scope of the present invention, asexpressed in the following claims.

1. A low voltage amplifier configured for increased compliance, said lowvoltage amplifier comprising: an input stage comprising a differentialpair of transistors configured to provide a first difference signal anda second difference signal; an output stage configured to receive atleast one of said first difference signal and said second differencesignal, said output stage comprising a first output device driven by aclass-AB control loop and only an upper direct signal path, and acomplementary, second output device driven by a lower direct signal pathsuch that voltage changes occurring at a gate of said complementary,second output device do not significantly affect load impedance realizedby said at least one of said first difference signal and said seconddifference signal from said output stage.
 2. The low voltage amplifieraccording to claim 1, wherein said class-AB control loop of said outputstage further comprises: a first biasing device, a first signal deviceand a second signal device, said first signal device having a gateconnected to a gate of said first biasing device and a drain connectedto said gate of said complementary, second output device, said secondsignal device having a gate connected to a control terminal of saidfirst output device, and said first signal device and said second signaldevice having sources configured for receiving said second differencesignal.
 3. The low voltage amplifier according to claim 2, wherein saidoutput stage further comprises: a gain configuration comprising a secondbiasing device, a third signal device and a fourth signal device, saidsecond biasing device and said third signal device having a gateconnected to a gate of said fourth signal device, said third signaldevice and said fourth signal device having sources configured forreceiving said first difference signal, and said fourth signal devicehaving a drain connected to a gate of said first output device.
 4. Thelow voltage amplifier according to claim 1, wherein said output stagefurther comprises a current mirror providing a signal path for saidsecond difference signal from said input stage to said output stage. 5.The low voltage amplifier according to claim 4, wherein said outputstage further comprises a charge pump coupled to said mirror tofacilitate compliance requirements of devices within said class-ABcontrol loop.
 6. The low voltage amplifier according to claim 3, whereinsaid third signal device and said fourth signal device having sourcescoupled to a current source configured to have increased compliancevoltage during signal mode ranging between approximately 1 volt toapproximately 300 mV.
 7. The low voltage amplifier according to claim 1,wherein said input stage comprises a first current source coupled tosources of said differential pair of transistors.
 8. The low voltageamplifier according to claim 7, wherein said amplifier comprises acharge pump coupled through said first current source to said inputstage.
 9. The low voltage amplifier according to claim 3, wherein saidamplifier is configured with an external feedback path to providedifferences in said first difference signal and said second differencesignal to regulate voltage at a node coupled to said gate of said secondoutput device.
 10. The low voltage amplifier according to claim 9,wherein said differences in said first difference signal and said seconddifference signal are amplified by said gain configuration.
 11. Anoutput stage for use in a low voltage amplifier configured for increasedcompliance, said output stage comprising: a first signal device and asecond signal device configured to receive a second difference signalfrom an input stage, said first signal device and said second signaldevice configured in a class-AB control loop configuration; a firstoutput device driven by said class-AB control loop and a first directsignal path; a third signal device and a fourth signal device configuredto receive a first difference signal from an input stage, and a secondoutput device complementary to said first output device, said secondoutput device driven only by a second direct signal path such that saidsecond output device operates at a low voltage during quiescent modeoperation.
 12. The output stage according to claim 11, wherein saidoutput stage further comprises: a first biasing transistor configuredwithin said class-AB control loop, said first signal device having acontrol terminal connected to a control terminal of said first biasingtransistor and an output terminal connected to said control terminal ofsaid second output device, said second signal device having a controlterminal connected to a control terminal of said first output device,and said first signal device and said second signal device having inputterminals configured for receiving said second difference signal. 13.The output stage according to claim 12, wherein said output stagefurther comprises: a second biasing transistor, said second biasingtransistor and said third signal device having a control terminalconnected to a control terminal of said fourth signal device, said thirdsignal device and said fourth signal device having input terminalsconfigured for receiving said first difference signal, and said thirdsignal device having an output terminal connected to a control terminalof said first output device.
 14. The output stage according to claim 13,wherein said fourth signal device having an output terminal connected tosaid control terminal of said second output device.
 15. An operationalamplifier comprising a folded cascode amplifier configured for operationat low voltages, said folded cascode amplifier comprising: a input stageconfigured for receiving current from a first current source and forproviding a first difference signal and a second difference signal; andan output stage comprising: a first output device coupled to an outputterminal; a second output device coupled to said output terminal; aclass-AB control loop and a direct signal path configured forcontrolling said first output device; and a gain configuration forcontrolling said second output device to enable said second outputdevice to operate with a low gate-source voltage.
 16. The operationalamplifier according to claim 15, wherein said operational amplifierfurther comprises a charge pump coupled to said input stage.
 17. Theoperational amplifier according to claim 15, wherein said input stagecomprises a differential pair of transistors configured to receive adifferential input voltage and to provide said first difference signaland said second difference signal.
 18. The operational amplifieraccording to claim 15, wherein said class-AB control loop comprises: afirst signal device and a second signal device configured to receivesaid second difference signal from said input stage; and a first biasingtransistor, said first signal device having a control terminal connectedto a control terminal of said first biasing transistor and an outputterminal connected to said control terminal of said second outputdevice, said second signal device having a control terminal connected toa control terminal of said first output device, and said first signaldevice and said second signal device having input terminals configuredfor receiving said second difference signal.
 19. The operationalamplifier according to claim 18, wherein said gain configurationcomprises: a third signal device and a fourth signal device configuredto receive said first difference signal from said input stage; and asecond biasing transistor, said second biasing transistor and said thirdsignal device having a control terminal connected to a control terminalof said fourth signal device, said third signal device and said fourthsignal device having input terminals configured for receiving said firstdifference signal, and said third signal device having an outputterminal connected to a control terminal of said first output device.20. The operational amplifier according to claim 18, wherein said outputstage further comprises a current mirror configured to receive saidsecond difference signal to provide to said first signal device and saidsecond signal device.